Nuts and Volts - May 2014

I just made the statement, " ... hang on the buss" and it should get a little explanation. The I2C physical layer defines the SCL and SDA lines as open-drain; these lines are intended to be pulled up to Vdd (typically through 4.7K to 10K). To output a one, the device floats the pin (makes it an input); this allows the pull-up to pull the line high (1). To output a zero, the device makes the pin an output and low (0).

The reason for this is electrical safety. If two devices attempt to write at the same time, the transmission will be clobbered, but with neither driving the line high while the other is actively pulling it low, there is no danger of a short circuit between devices.

Here's the rub ... the Propeller boot loader violates this specification. If you look on some older Propeller designs, you'll see that the SCL line is missing a pull-up. The reason is that the Propeller boot loader assumes the only thing connected to it is an EEPROM and it's safe to drive the clock line high and low. This isn't going to change in the Propeller because the boot loader is masked into the chip.

Don't let this worry you, though; I've built lots and lots of boards and never had an I2C device failure. Rest assured that newer Propeller designs from Parallax — like the Propeller Activity Board which is one of my favorite little development tools — have a pull-up on SCL, as well as SDA.

Please ... in your own designs, you should put the pull-up on the SCL pin because most I2C code counts on it. For reference, Figure 1 shows the EEPROM connections from my project starter schematic (the Dip Trace file is included with the downloads). If you have an older board without the SCL pull-up, there is an excellent I2C object by Mike Green that does drive the SCL line high and low.

Okay, then. Let's get into the nuts and bolts of I2C communications. An I2C transaction is built from four elements: • Start condition • Write byte(s)

• Read bytes(s)

• Stop condition Yes, that's really it. Everything else is built with these functional blocks.

When the I2C master (Propeller) is instantiated, the SCL and SDA pins are set to input mode which allows the pull-ups to take both lines high. A Start condition (notated with an S in I2C transaction diagrams) is created by taking the SDA line low while the SCL line remains high (Figure 2).

Write and Read transactions are byte-oriented, but use nine clock cycles (Figure 3). The ninth clock is for the Acknowledge bit provided by the receiving end of the transaction. The master provides all clock cycles.

When writing a byte, each bit is output to the SDA line (MSBFIRST) and then the SCL line is taken high (via the pull-up), then back low. After the eighth bit, the SDA line is set to input mode and the clock is taken back high. At this point, the master samples the SDA line for ACK (0) or NAK (1).

The Read transaction is similar except the SDA line is in input mode for the first eight bits. The leading edge of the clock signal causes the slave to output a bit which is then sampled by the master. After the eighth bit, the master will output the appropriate ACK/NAK bit for the slave and pulse the clock a final time.

The Stop condition (notated with a P in I2C transaction diagrams) is created by allowing the SDA line to go high while the clock line is already high. Note that the Stop condition is — at times — used in the middle of a transaction. We'll see this in detail later.