Nuts and Volts - March 2015

bit binary counter bank, and an input switch (74AS00) to allow the PIC to control the input clock source. This building block is used as the gate signal generator and as the input counter.

The 74F579 is designed for bus operation. Its data outputs are tri-state, and are also used as inputs to preset the counter. Operation of the IC uses three control pins: CS’ – Chip Select; PE’ – Parallel (input) Enable; and OE – Output Enable’ (the ‘ indicates logic low active). The PIC can address each of the 74F579s by setting its CS’ pin to a logic low (0), and setting either PE’ low to preset the chip flip-flops or OE’ low to read the chip flip-flops. So, to preload the counter banks, the PIC sequentially performs a CS’/PE’ pair individually for each of the three 74F579s in each bank. An additional U/D’ pin on the 74F579 controls the counting direction. I set both banks to count up.

The 74F579 is a synchronous counter. To understand what this means, we have to look at how a traditional ‘ripple’ counter works. In a ripple counter, each flip-flop output is the clock input to the next stage so that the delay adds up as the stages add up. For example, if the delay between the clock input and the change in output state of the flip-flop is five nanoseconds, then since the flip-flop output is the clock input to the next stage, the delay of the second flip-flop is 5 + 5 nanoseconds. This delay ‘ripples’ through the counter. In a 24-stage counter, the delay at the last stage is 5 x 24, or 120 nanoseconds. Unfortunately, this delay may vary over a two (or three) to one range just due to production variances. A synchronous counter removes the ripple effect by having each stage clocked by the same clock. The synchronous counter operation is necessary for accurate gate timing, but it’s not sufficient. The gate timing must also start and stop on a clock edge. This is the reason for the gate synchronizer (Figure 3) which uses a 74F74 dual flip-flop. I’ll go through the process of making a simple one second frequency measurement to illustrate the gate operation. Note (as mentioned) that the gate counter is set to count up, so we set it to a value that is minus the desired count. First, the PIC presets the gate and counter banks. The counter bank is set to zero (effectively a reset operation) and the gate bank is set to minus 10,000,255 (see below). Normally, the START line is logic low, with U6A in the reset state and U6B in the set state. The PIC starts a frequency reading by first selecting the internal reference as the gate clock and the input signal as the counter input. The PIC then sets START to a one. At the next internal reference clock pulse, U6A sets since U6B is already set. The AND gate enables the CET’ pin on both counter banks, thereby starting the counting. The TC’ pin of the third stage of the gate counter goes low 256 clock pulses before the gate bank reaches its terminal count. This TC’ is connected to the D input of U6B. On the next gate clock pulse, U6B is reset thus turning off the gate. I had to preset the gate bank to minus 10,000,255

24 March 2015

■ FIGURE 3. Gate synchronizer schematic.

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