the PIC that is toggled high/low to simulate a clock pulse.
The PIC then sets port D as an output, pulses the Master
Clear pin on U3 setting the RAM address at 00000000,
and then places the RAM data on the buss.
The PIC then toggles the Write Enable on the RAM to
store the location 00000000 function data. The PIC then
toggles PICCKC to advance U3 to RAM location
00000001, and repeats the storing sequence until all RAM
locations are filled.
The frequency counter generally follows the traditional
model where a fixed gate interval (say, one second) is set
using a PIC counter (TIMER2) running off the 10 MHz
clock. A second PIC counter ( TIMER1 – RC0 input) counts
the number of input cycles during that interval. With a
one second gate, the number of input cycles is equal to
the input frequency (with a ±1 count error).
This works very well if the input frequency is high
because the ±1 count error can be ignored. However, to
accurately measure a low input frequency, the gate
interval must either be increased, or the counter can be
set to measure the period of the input signal.
With the latter technique, the roles of TIMER1 and
TIMER2 are sort of reversed. TIMER1 still sets the gate
interval and still counts the input cycles, but it’s
programmed to count a specific whole number of input
cycles so there is no ±1 error here. Meanwhile, TIMER2
counts the 10 MHz system clock during this gate interval;
it has the ±1 count error but the error is one in 10 million
(the system 10 MHz
For example, if the
input signal is 1 MHz,
then using the
counter model and a
one second gate
interval, the error will
be ±1 input count in
one million — not bad.
If the input signal is
100 Hz, the ±1 count
is one in 100 — not
very good. If we
instead set the gate
interval to be exactly
100 input cycles (one
second), TIMER2 will
read 10 million ±1
count — excellent.
In my design, I
automatically switch to
a period measurement
when the input frequency is less than 150,000 Hz. I do
this by making a preliminary measurement of the input
frequency using a 0.1 second gate interval. If the
frequency is greater than 150,000 Hz, I do a one second
final frequency measurement. Otherwise, I switch to a
period measurement. With this technique, I get frequency
measurements accurate to five/six digits every 1.1 seconds
over the entire frequency range of 10 Hz to over 10 MHz.
I want the period measurement to last for about one
second. From the .1 second frequency trial measurement,
we get an approximate value for the input frequency —
say, 99 Hz. This means the input frequency is between 98
and 100 Hz (the ±1 count error). Assume the input
frequency is exactly 99.56 Hz. I set TIMER1 to 99 (for the
approximately one second gate time) and get the total
number of 10 MHz clock pulses in 99 pulses of the input
Since the input frequency is actually 99.56 Hz and it
has a period of .0100442 seconds, the total gate time will
be 99 x .0100442 or .994376 seconds.
Meanwhile, TIMER2 is counting the 10 MHz clock
(having a period of .0000001 seconds) and will end up
with .994376/.0000001 or 9,943,760 clock pulses for 99
input cycles. So, the actual period of the input signal is
( 9,943,760 x .0000001)/99 or .01004442 seconds, or
99.56 Hz — perfect!
There are many designs for a frequency counter input
amplifier available on the Internet (also check out the
design I used in the above referenced article). For this
project, I simply use an available inverter (U8f) which is
used for the high speed oscillator. To prevent any
32 November 2016
■ FIGURE 4.