standard data message (logic 0) or an RTR (logic 1).
Device 0x0C1 sends 0x0AF a standard message. A CAN
controller will send an RTR message to request
information from one or more devices. That transmission
includes an address but no data bytes. You program a
register bit to create an RTR message.
The CAN standard specifies a six-bit control field in
which the four LSBs hold the data-length-code (DLC) that
indicates the number of data bytes: 0 through 8 or 00002
to 10002. The original CAN standard reserved the two
MSBs in the control field for future use. In the latest
standard, one bit — labeled ID Extended — indicates
whether a frame uses a standard 11-bit or an extended 29-
bit identifier. One bit still remains reserved for future use.
Next, the CAN frame includes a 15-bit cyclic
redundancy code (CRC) value calculated by the sending
controller, followed by a logic 1 “delimiter” bit that ends
the CRC field. After the CRC-delimiter bit, the sender
transmits a recessive (logic 1) output and its receiver
monitors the bus. Whether or not specifically addressed,
all devices on the bus receive the frame and all calculate a
CRC based on the data they received. They all use the
same CRC algorithm.
Why do the “unaddressed” devices also need to
calculate the CRC? It helps them detect controller
problems. After the CRC calculations, each device
compares its result with the CRC in the received frame.
When the two match, a CAN device transmits a single-bit
dominant (logic 0) acknowledgment (ACK) signal on the
bus. If the CRCs do not match, a device puts out a one-bit
recessive (logic 1) state.
Assume all receiving devices work properly and all put
a logic 0 on the bus during the ACK period. The sender
monitors the bus and expects this logic 0 signal. So, no
CAN device reported an error and everything seems to
looks good. (Keep in mind the acknowledgment only
indicates a CRC match and not that a message was
Oops, a CRC Mismatch
What happens in a CAN controller when a received
CRC and a calculated CRC don’t match? This situation
provides a good example of the clever capabilities of CAN
communications you cannot get with simple UART
1. Say one CAN device (XYZ) calculates a CRC not
equal to the CRC in a message. That error will cause it to
keep its transmitter output in the recessive state during the
ACK period. At the start of the ACK period, device XYZ
detects a dominant state on the bus caused by other
receivers that have no CRC mismatch. The difference
between the dominant “CRC-OK” signal on the bus and
recessive “CRC-mismatch” signal from device XYZ causes
it to send an error frame (Figure 7) right after the ACK
2. Now consider the case when all devices on a bus
detect a CRC error. They all put a recessive signal on the
bus. The sender expects a “CRC-OK” dominant signal
instead. The recessive signal indicates the sender either
calculated an incorrect CRC or transmitted an incorrect
CRC. So, the sending device knows it has a problem and
reports an error.
Other types of errors can occur at other times and
also cause transmission of an error frame. The receipt of
an error frame may trigger a resend of the original
message. CAN controllers can count errors and cause an
interrupt if they exceed preset limits. However, the CAN
bus has proven very reliable and data errors rarely occur,
although you could experience signaling problems in a
poorly designed bus topology.
What’s an Error Frame?
As shown in Figure 7, an error frame comprises a
April 2017 33
1. "Non-Blocking Code," Engscope;
2. Titus, Jon, "The Hands-On XBee Lab Manual," Newnes
Press, Waltham, MA, USA. 2012, pp. 228-246. ISBN: 978-0-
3. Voss, Wilfried, "A Comprehensible Guide to Controller
Area Network," Copperhill Media, Greenfield, MA 2008.
ISBN: 978-0976511601; http://copperhilltech.com/technical-literature.
4. Microchip MCP2515 datasheet, DS21801G.
ARM Cortex-M3 Nested Interrupt Vector Controller (NVIC):
Reentrant Code Tutorial:
FIGURE 7. An error frame includes six dominant bits followed
by eight recessive bits in an error delimiter. Only an error frame
purposely puts this arrangements of bits on a CAN bus.