FIGURE 2. FPz8 block diagram.
Instruction Queueing Engine
IQUEUE.FETCH_STATE := F_READ;
if (IQUEUE.FULL=’0’) then
IQUEUE.QUEUE(IQUEUE.WRPOS) := IDB;
FETCH_ADDR := FETCH_ADDR + 1;
IAB <= FETCH_ADDR;
IQUEUE.WRPOS := IQUEUE.WRPOS + 1;
IQUEUE.CNT := IQUEUE.CNT + 1;
if (IQUEUE.CNT=7) then IQUEUE.FULL:=’1’; else
Fetching instructions is a primary task for any CPU. The
FPz8’s Harvard architecture enables concurrent fetching
and data access (due to separate buses for instruction and
data). That means the CPU can fetch a new instruction
while another is reading or writing into data memory.
The eZ8 has a variable length instruction word
(instruction length varies from one byte up to five bytes);
some instructions are lengthy but run faster than others.
That way, a BRK instruction has a length of one byte and
runs in two cycles, while an LDX IM,ER1 is four bytes long
and runs in two clock cycles.
So, how can we successfully decode all these
instructions? With an instruction queue; that is, a
mechanism that keeps fetching bytes from program
memory and storing them into an eight-byte array:
Listing 1. Instruction queue engine.
if (CAN_FETCH=’1’) then
if (IQUEUE.FETCH_STATE=F_ADDR) then
FETCH_ADDR := PC;
IAB <= PC;
IQUEUE.WRPOS := 0;
IQUEUE.RDPOS := 0;
IQUEUE.CNT := 0;
Fetching is controlled by a main enable signal
(CAN_FETCH) which can be disabled in some special
cases (interrupt processing, by LDC/LDCI instructions or
debugger access). There is also a structure (IQUEUE) which
stores several internal parameters (fetching state, read
and write pointers, queue array itself, a counter, and a full
The queue counter (CNT) is used to identify the
number of bytes available for use (reading) in the queue.
The decoder stage uses this number to verify that the
desired number of bytes for the instruction is already
available in the queue.
44 July 2017