Nuts and Volts - February 2018

important. Speed is defined as the time it takes for the DAC to change its output voltage in response to a change at its digital input. A perfect DAC would have zero conversion time, but reality falls short. The rise times, fall times, and settling times of the DACs are important to the AGI project as they define the rate that can be used to send points to the scope screen; this, in turn, sets the maximum number of points we can display within our target POV window of 20 ms.

Since DAC speed is not specified in the ATMEL SAM datasheet, I wrote a small AGI program to drive the DACs from 0 to 4095 and then back to 0, so that I could make my own “worst case” full-scale speed measurements.

Using an oscilloscope to monitor the DAC outputs,

Figure 4 shows that a full-scale change in output of the DAC from 0 to 4095 in one step takes slightly over 300 ns. Similarly, the step going from 4095 back to 0 is seen to be about 300 ns as well. Figure 4 also shows a few other aspects of the overall timing. First off, observe that the

DMA_CLK (TP17) signal (one of the Due Counter-Timers) drives the rate of the DMA transfers and therefore the pace of digital-to-analog conversions.

Next, note that the X and Y conversions follow each other in time, with the DAC0 signal (the X axis value) changing first, followed one DMA_CLK cycle later by the DAC1 signal (Y axis). Analog sample and hold circuits are used to time-synchronize the X and Y signals to one another before they are sent out to the oscilloscope as the X-Drive (TP8) and Y-Drive (TP9) signals for display.

Finally, the Z axis signal Z-Drive (TP10) is used to turn the CRT Spot on (logic 1 = “unblank”) every time a new point pair is ready for display on the screen. The CRT Spot is then turned off (logic 0 = “blanked”) just before the X-Y signals are “moved” to the next point to be plotted. Blanking the beam in this way keeps the display crisp and free of DAC settling times and other point-to-point transition artifacts.

Given the DAC rise and fall times, it’s possible to determine the highest DMA_CLK frequency we can use. My tests show reliable high quality graphics plotting can be achieved at DMA_CLK frequencies up to 800 kHz. Above 800 kHz, the DAC rise and fall time delays begin to distort the graphics display, appearing as incorrectly plotted points on the oscilloscope screen whenever adjacent members in the XY list are far away from one another.

Using a Timer to Trigger CRT Refresh

As noted, we need to repeat the DMA transfer over and over again to keep the CRT scope screen lit up. To do this, the AGI uses a second timer to create a “ Time-to-Refresh” interrupt once every 20 ms. Every time we receive this interrupt, a new CRT screen-paint cycle is initiated. This repaints the screen 50 times per second, above discernable POV flicker rates.