By the NTSC specification, the action-safe
area is defined as 93 percent of the total picture.
Because we are running a 12. 5 MHz pixel clock
and generating 658 active pixels, this results in 612
action-safe pixels. To make the math easier, let’s
shrink that to 600 horizontal pixels.
We need to retain the 4: 3 aspect ratio of a
standard definition television. This leaves us with a
vertical resolution of 450 lines, which is exactly 93
percent of 484 vertical lines! Our final resolution is
600x450, which is a bit non-standard. That’s okay! If
you look at past video game systems and computers
that output NTSC, they all ran at non-standard
resolutions.
SRAM Interface
Enough with that cryptic NTSC video standard!
Time to move on to the SRAM, which is a bit easier
to manage. I suggest you follow along with the
device’s datasheet while reading this section. The
SRAM Chip Enable (#CE) signal is hard-wired low
on the shield to enable continuous selection. This
simplifies the SRAM controller logic and because
of this, a read operation depends entirely on the
Output Enable (#OE) signal. Data is available 10 ns after
an address change. However, it’s not valid until 4. 5 ns after
#OE transitions low.
The write operation is a little different. The address
must be stable for 0 ns before Write Enable (#WE)
transitions low. Yup, zero setup time! The WE signal must
then be held low for 8 ns and the address
must continue to remain stable for 2 ns
after WE transitions high. This translates
to a minimum write cycle time of 10 ns.
The exact details of the SRAM controller
module will be outlined later in the article.
Verilog Design
We are done with the hardware! Time
to talk about the Verilog logic. The NTSC
module (ntsc.v) consists of a pixel clock
(pixel_clock.v) and a sync/pixel generator
(ntsc_sync.v). The pixel clock divides the
50 MHz Mojo V3 clock by four and emits
a 20 ns tick at 12. 5 MHz. This keeps the
sync/pixel generator synchronous with the
Mojo V3 master clock. That’s pretty simple!
Unfortunately, the sync/pixel generator is a
bit more complicated.
The sync/pixel generator outputs the
current pixel coordinates as well as the
horizontal and vertical synchronization
signals. To accomplish this, it keeps track of
the current horizontal sample and vertical line in a pair of
registers (h_count_ff and line_ff).
Let’s look at some important sample and line numbers.
For horizontal synchronization:
• Front Porch: 19 samples / 1.52 µs
Figure 6. Horizontal
synchronization and
active video.
C1, C2, C3, C5, C7, C10, C11 0.1u 445-14600-1-ND
C4 27p 399-9341-1-ND
C6, C8 10u 478-8150-1-ND
C9 0.01u 445-14599-1-ND
J1 MD-40SM CP-2240-ND
J2 RCJ-014 CP-1403-ND
L1 68u 445-15774-1-ND
R1, R3, R6 510 311-510ERCT-ND
R2, R4, R7 1K 311-1.0KERCT-ND
R5, R8 2K 311-2.0KERCT-ND
R9, R10, R11 75 311-75ERCT-ND
R12, R14, R16 374 311-374FRCT-ND
R13, R15, R17 301 311-301FRCT-ND
U1 AD723ARU AD723ARUZ-ND
U2 ASV- 14.31818MHZ-EJ-T 535-9310-1-ND
U3 AS7C38096A-10TIN 1450-1067-ND
Stackable Headers Embedded Micro Digi-Key Part #s
September/October 2018 73
